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stv0042a/z analog satellite sound and video processor ? september 2003 1/37 sound features n two independent sound demodulators n pll demodulation with 5-10 mhz frequency synthesis n programmable fm demodulator bandwidth accommodating fm deviations between 30 and 400 khz n programmable 50/75 s or no de-emphasis n dynamic noise reduction (anrs) n one or two auxiliary audio inputs and outputs n gain-controlled and mutable audio outputs n high-impedance mode audio outputs for twin tuner applications video features n composite 6-bit video with 0 to 12.7 db gain control n selectable composite video inverter n two selectable video de-emphasis networks n 4 x 2 video matrix n high-impedance mode video outputs for twin tuner applications miscellaneous features n 22 khz tone generation for lnb control n i2c bus control: chip addresses = 06h n low power stand-by mode with active audio and video matrices general description the stv0042 bicmos integrated circuit is designed for low-cost analog satellite receiver applications. the stv0042a/z performs all the necessary signal processing from the tuner to the audio/video input and output connectors regardless of the satellite system. shrink42 (shrink plastic dual in-line package) order code : stv0042a/z
stv0042a/z 2/37 table of contents chapter 1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 pin description ......................................................................................................... ......... 3 chapter 2 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 chapter 3 input/output diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 chapter 4 i2c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1 writing to the chip ........................................................................................................ ...... 19 4.2 reading from the chip ...................................................................................................... .19 chapter 5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 chapter 6 fm demodulation software routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 6.1 detailed description ... ........................................................................................................ 25 chapter 7 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 chapter 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 8.1 absolute maximum ratings .............................................................................................. 30 8.2 thermal data .............................................................................................................. ...... 30 8.3 electrical characteristics ................................................................................................. ... 30 chapter 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 chapter 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 6
3/37 stv0042a/z general information 1 general information 1.1 pin description figure 1: pin connections table 1: pin description (sheet 1 of 2) pin no. name function 1 fcr audio roll-off right 2 pkin noise reduction peak detector input 3 sumout noise reduction summing output 4 volr right volume-controlled audio output 5 s1vidout tv scart video output 1 6 s2vidout vcr scart video output 2 7 voll left volume-controlled audio output agndr fcl pkout iref cpumpr u75r detr amplkr a12v vref agndl agcr amplkl u75l detl cpumpl gnd5v vdd5v xtl sda scl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 fcr pkin sumout volr s1vidout s2vidout voll s2vidrtn s2outl clampin s2outr uncldeem videem2/22khz v12v videem1 vgnd bbandin s2rtnl s2rtnr fmin agcl
general information stv0042a/z 4/37 8 s2vidrtn vcr scart video return 2 9 s2outl left fixed level audio output 10 clampin sync tip clamp input 11 s2outr right fixed level audio output 12 uncldeem unclamped de-emphasized video output 13 videem2/22khz video de-emphasis 2 or 22 khz output 14 v12v 12 v video power supply 15 videem1 video de-emphasis 1 16 vgnd video ground 17 bbandin base band input 18 s2rtnl left auxiliary audio return 19 s2rtnr right auxiliary audio return 20 fmin fm demodulator input 21 agcl left agc peak detector capacitor 22 scl i2c bus clock 23 sda i2c bus data 24 xtl 4/8 mhz crystal oscillator or clock input 25 vdd5v digital 5 v power supply 26 gnd5v digital ground 27 cpumpl left fm pll charge pump capacitor 28 detl left fm pll filter 29 u75l left de-emphasis time constant 30 amplkl left amplitude detector capacitor 31 agcr right agc peak detector capacitor 32 agndl left audio ground 33 vref 2.4 v reference power supply 34 a12v 12 v audio power supply 35 amplkr right amplitude detector capacitor 36 detr right fm pll filter 37 u75r right de-emphasis time constant 38 cpumpr right fm pll charge pump capacitor 39 iref current reference resistor 40 pkout noise reduction peak detector output 41 fcl left audio roll-off 42 agndr right audio ground table 1: pin description (sheet 2 of 2) pin no. name function
5/37 stv0042a/z general information 1.1.1 sound detection 1.1.1.1 fm demodulators a block diagram of the fm demodulation block is shown in figure 3 . pin fmin (pin 20) is the input to the two fm demodulators. it feeds two agc amplifiers with a bandwidth of at least 5 to 10 mhz. there is one amplifier for each channel. both channels have the same input. the agc amplifiers have a range between 0 and +40 db. the input impedance (z in ) is 5 k w with a minimum input of 2 mv pp per subcarrier and a maximum input of 500 mv pp . this is the maximum value when all inputs are added together, when their phases coincide. 1.1.1.2 agc peak detector capacitors pins agcl and agcr (pins 21 and 31, respectively) are the agc amplifier peak detector capacitor connections. the output current has an attack/decay ratio of 1:32. this means that the ramp-up current is approximately 5 a and decay current is approximately 160 a. 11v gives maximum gain. these pins are also driven by a circuit monitoring the voltage on pins amplkl and amplkr, respectively. 1.1.1.3 amplitude detector capacitors pins amplkl and amplkr (pins 30 and 35, respectively) are the left and right outputs of their respective amplitude detectors. each pin requires a capacitor and a resistor to gnd. the voltage across these pins is used to decide whether a signal is being received by the fm detector. the level detector output drives a bit in the i2c bus detector control block. pins amplkl and amplkr drive also respectively pins agcl and agcr. for instance, when the voltage on pin amplkl is > (v ref + 1 v be ) it sinks current to v ref from pin agcl in order to reduce the agc gain. figure 2: stv0042a/z general block diagram stv0042a/z from tuner from tuner from vcr/decoder 22 khz to lnb b-band video processing fm demodulation 2 channels noise reduction & de-emphasis 4 x 2 video matrix audio matrix & volume i2c bus interface to tv vcr decoder 2 2 active in standby mode 2 2 1
general information stv0042a/z 6/37 1.1.1.4 fm pll filters pins detl and detr (pins 28 and 36, respectively) are the left and right outputs of their respective fm phase detectors. these pins are used to connect an external pll loop filter. the output is a push-pull current source. 1.1.1.5 fm pll charge pump capacitors pins cpumpl and cpumpr (pins 27 and 38, respectively) are the fm pll charge pump capacitors. the output from the frequency synthesizer is a push-pull current source which requires capacitors to pull each vco to the target frequency. the output is 100 a to achieve lock and 2 a during lock to provide a tracking time constant of approximately 10 hz. in order to prevent a false locking in certain marginal conditions, it is best to add a 8.2 v zener diode to pins cpumpl and cpumpr. figure 3: fm demodulation ag c level d e t e c tor 1 level d e t e c tor 2 fm in ag c r a m p l k r v r e f r eg8 b4 bias 90 0 v c o a u d i o r d e t r c p u m p r sy n t h e s i z e r stv0042a/z a mp. d e t e ct s w 1 p h as e d e t e ct v r e f fm d e v . s e l e ct. s w 4 s w 2 ag c level d e t e c tor 1 level d e t e c tor 2 ag c l a m p l k l v r e f bias 90 0 v c o a u d i o l d e t l c p u m p l a mp. d e t e ct s w 3 p h as e d e t e ct v r e f fm d e v . s e l e ct. w a t c h do g w a t c h do g r eg8 b 0 s w 5 r l
7/37 stv0042a/z general information 1.1.1.6 voltage reference pin vref (pin 33) is the audio processor voltage reference used throughout the fm/audio section of the chip. this pin must be correctly decoupled from to ground in order to reduce as much as possible the risk of crosstalk and noise injection. this voltage reference is directly derived from the bandgap reference of 2.4 v. the v ref output can sink up to 500 a in normal operation and 100 a when in standby mode. 1.1.1.7 current reference resistor pin iref (pin 39) is a buffered v ref output to an off-chip resistor used to produce an accurate current reference, within the chip, for the biasing of amplifiers with current outputs into filters. it also provides accurate roll-off frequencies for the noise reduction circuit. this pin should not be decoupled as this would inject current noise. the target current is 50 a 2%, therefore a 47.5 k w 1% resistor is required. 1.1.1.8 12 v audio power supply pin a12v (pin 34) is a double-bonded main power pin used by the audio/fm section of the chip. the two bond connections are used for the esd and to power the circuit and on-chip regulators/ references. 1.1.1.9 audio ground pins agndl and agndr (pins 32 and 42, respectively) are double-bonded ground pins. 1.1.2 baseband audio processing 1.1.2.1 noise reduction peak detector the noise reduction control loop peak detector output (pkout pin (pin 40)) is connected to a capacitor to ground and to a resistor to the vref pin in order to provide an accurate decay time constant. an on-chip 5 k w 25% resistor and external capacitor give the attack time. pin pkin (pin 2) is an input to a control loop peak detector and is connected to the output of the off- chip control loop band pass filter. 1.1.2.2 noise reduction summing output a 0.5-gain amplifier is used to sum together the two audio demodulated signals. this value is then output on pin sumout (pin 3). for example, if both inputs are equal to 1 v, then the output is 1 v. this amplifier has an input follower buffer which provides a v be offset in the dc bias voltage. therefore, the filter driven by this amplifier must include ac coupling to the next stage (pin pkin). 1.1.2.3 audio roll-off the variable bandwidth transconductance amplifier has a current output which is variable depending on the input signal amplitude as defined by the anrs control loop. the output current is then dumped into an off-chip capacitor which together with the accurate current reference define pin pad 1 pad 2 agndl left channel: rf section and vco both agc amplifiers, channel left and right audio filter section. agndr right channel: rf section and vco volume control, noise reduction system, esd + multiplexer + v ref
general information stv0042a/z 8/37 the minimum/maximum roll-off frequencies. a resistor in series with a capacitor is connected to the ground via pins fcl and fcr (pins 41 and 1, respectively). 1.1.2.4 de-emphasis time constants pins u75l and u75r (pins 29 and 37, respectively) are external de-emphasis networks for left and right channels. for each channel, a capacitor and resistor in parallel with a 75 s time constant are connected to the v ref to provide a 75 s de-emphasis. an internal resistor can be programmed to be added in parallel thereby converting the network to approximately 50 s de-emphasis. the value of the internal resistors is 30 k w 30%. the amplifier for this filter is voltage input, current output; with 500 mv input the output will be 55 a. 1.1.2.5 volume-controlled audio outputs pins voll and volr (pins 7 and 4, respectively) are the main audio outputs from the volume control amplifier. output signals may be as high as 2 v rms (+12 db) with a dc bias of 4.8 v. the volume control is between +12 db and -26.75 db in steps of 1.25 db with possible mute. this amplifier has short-circuit protection and is intended to drive a scart connector directly via ac coupling and meets the standard scart drive requirements. these outputs feature high impedance mode for parallel connections. 1.1.2.6 fixed-level audio outputs pins s2outl and s2outr (pins 9 and 11, respectively) are audio outputs that are directly sourced from the audio multiplexer, and as a result do not include any volume control functions. they will output a 1 v rms signal biased at 4.8 v. they are short-circuit protected. these outputs feature high impedance mode for parallel connections and meet scart drive requirements. figure 4: audio switching k 2 k 3 a b 1 b 2 on on on no anrs, no de-emphasis no anrs, 50 s no anrs, 75 s a b 1 b 2 off off off anrs, no de-emphasis anrs, 50 s anrs, 75 s audio deemphasis + anrs vol out aux out audio pll aux in k 1a k 5b k 5c k 5a k 1c
9/37 stv0042a/z general information 1.1.2.7 auxiliary audio returns pins s2rtnl and s2rtnr (pins 18 and 19, respectively) allow auxiliary audio signals to be connected to the audio processor and therefore make use of the on-chip volume control. for additional details please refer to the audio switching table. figure 5: audio signal processing diagram (left) stv0042a/z pk ou t pk in s u m ou t fc l a u d i o d ee m p h a s i s s 2 r t n l u 75 l d e t l p ll f i l t e r 5 k 3 k 2 a k 1 a c b b c k 5 m o n o s t e r e o s 2 ou t l v o l l t v a u d i o l a n r s d e c o d e r o r v c r a b 2 8 1 8 40 2 3 1 4 1 2 9 9 7 6d b fc r - 6d b
general information stv0042a/z 10/37 1.1.3 video processing a block diagram of the video processing block is shown in figure 7 . 1.1.3.1 base band input pin bbandin (pin 17) is an ac-coupled video input from a tuner with an impedance greater than 10 k w 25%. this pin drives an on-chip video amplifier. the other input of this amplifier is ac grounded via an internal connection to pin vref. the video amplifier has selectable gain from 0 db to 12.7 db in 63 steps and its output signal can be selected as normal or inverted. 1.1.3.2 unclamped de-emphasized video output pin uncldeem (pin 12) is an unclamped de-emphasized video output. it is also an input of the video matrix. 1.1.3.3 sync tip clamp input pin clampin (pin 10) clamps the extreme negative values (the sync tips) of the input signal to 2.7 v dc (or the appropriate voltage). the video at the clamp input is only 1v pp . this clamped video which is de-emphasized, filtered and clamped (energy dispersal removed), is a normal video signal with negative synchronization. this signal drives the video matrix input called normal video. it has a weak (1.0 a 15%) stable current source pulling the input towards the ground. otherwise, the input impedance is very high at dc to 1 khz z in > 2 m w . video bandwidth through this pin is -1 db at 5.5 mhz. the clamp input dc restore voltage is then used to obtain the correct dc voltage on the scart outputs. 1.1.3.4 video de-emphasis 1 pin videem1 (pin 15) is connected to an external de-emphasis network (for instance, 625 lines pal de-emphasis). figure 6: audio signal processing diagram (right) stv0042a/z pk ou t pk in s u m ou t fc l a u d i o d ee m p h a s i s s 2 r t n r u 75 r d e t r p ll f i l t e r 5 k 3 k 2 a k 1 a c b b c k 5 m o n o s t e r e o s 2 ou t r v o l r t v a u d i o r a n r s d e c o d e r o r v c r a b 3 6 1 9 40 2 3 1 4 1 3 7 11 4 6 d b fc r - 6 d b
11/37 stv0042a/z general information 1.1.3.5 video de-emphasis 2 or 22 khz output pin videem2/22khz (pin 13) is connected to an external de-emphasis network (for instance, 525 lines ntsc or other video de-emphasis). alternatively, a precise 22 khz tone may be output by i2c bus control. 1.1.3.6 vcr scart video return pin s2vidrtn (pin 8) is an external video input 1.0 v pp ac-coupled 75 w source impedance. this input has a dc restoration clamp on its input. the clamp sink current is 1 a 15% with the input buffer impedance greater than 1 m w . this is the input signal to the video matrix. 1.1.3.7 scart video outputs pins s1vidout and s2vidout (pins 5 and 6, respectively) are video drivers for scart 1 and scart 2. an external emitter follower buffer is required to drive a 150- w load. the average dc voltage must be 1.5 v on the outputs. the video signal is 2.0 v pp with a 5.5 mhz bandwidth with 1.2 v sync tips. these pins receive the signals sent from the video matrix. the signal that will be output from the video matrix is controlled by a control register. these outputs also feature high impedance mode for parallel connections. 1.1.3.8 12v video power supply pin v12v (pin 14) is a double-bonded 12-v video power supply with esd and guard rings. 1.1.3.9 v gnd pin vgnd (pin 16) a strategically placed double-bonded video power ground connection used to reduce video currents getting into the rest of the circuit.
general information stv0042a/z 12/37 1.1.4 control block 1.1.4.1 5-v ground pin gnd5v (pin 26) is the main power ground connection for the control logic registers, the i2c bus interface, synthesizer, watchdog and the crystal oscillator. 1.1.4.2 5-v digital power supply pin vdd5v (pin 25) is a digital 5-v power supply. 1.1.4.3 scl this pin (pin 22) is the i2c bus clock line. it requires an external pull-up (for example, 10 k w at 5v). clock = dc to 100 khz. 1.1.4.4 sda this pin (pin 23) is the i2c bus data line. it requires an external pull-up (for example, 10 k w at 5v). 1.1.4.5 4/8 mhz quartz crystal or clock input pin xtl (pin 24) allows the on-chip oscillator to be either used with a 4 mhz or 8 mhz crystal oscillator connected to ground or to be driven by an external clock source. the external source can be either 4 mhz or 8 mhz. a programmable bit in the cont rol block removes a ? 2 block when the 4 mhz option is selected. figure 7: video processing block diagram clam p clam p normal v c r / dec o de r retu r n t o dec o de r or v c r t o t v s1 v i d ou t s 2 v i d ou t s 2 v i d r t n clam p i n g b-b a n d i n stv0042a/z 22 kh z t o n e b a s e b a nd l p f v i d ee m 1 v i d ee m 2 / 22 kh z u n cl d ee m n t s c p a l dee m ph a s i z ed 1 1 7 1 3 1 5 1 2 5 6 8 1 0 2
13/37 stv0042a/z circuit description 2 circuit description 2.0.1 video section the composite video is first set to a standard level by means of a 64-step gain-controlled amplifier. if the modulation is negative, an inverter can be switched in. one of two different external video de-emphasis networks (for instance pal and ntsc) is selectable by an integrated bus controlled switch. then energy dispersal is removed by a sync tip clamping circuit, which is used on all inputs to a video switching matrix, thus making sure that no dc steps occur when switching video sources. the matrix can be used to feed video to and from decoders, vcrs and tvs. additionally, all the video outputs are tri-state type (high impedance mode is supported), allowing a simple parallel connections to the scarts (twin tuner applications). 2.0.2 audio section the two audio channels are totally independent except for the possibility given to output on both channels only one of the selected input audio channels. to allow a very cost-effective application, each channel uses pll demodulation. neither external complex filter nor ceramic filters are needed. the frequency of the demodulated subcarrier is chosen by a frequency synthesizer which sets the frequency of the internal local oscillator by comparing its phase with the internally generated reference. when the frequency is reached, the microprocessor switches in the pll and the demodulation starts. at any moment the microprocessor can read from the device (watchdog registers) the actual frequency to which the pll is locked. it can also verify that a carrier is present at the wanted frequency (by reading amplk status bit) thanks to a synchronous amplitude detector, which is also used for the audio input agc. in order to maintain constant amplitude of the recovered audio regardless of variations between satellites or subcarriers, the pll loop gain may be programmed from 56 values. any frequency deviation can be accommodated between 30 and 400 khz. in the typical application, the stv0042a/z offers two audio de-emphasis 75 s and 50 s. when required a j17 de-emphasis can be implemented by using specific application diagram (see application note: an838, chapter 4.2). a dynamic noise reduction system (anrs) is integrated into the stv0042a/z using a low-pass filter, the cut-off frequency of which is controlled by the amplitude of the audio after insertion of a bandpass filter. two types of audio outputs are provided: one is a fixed 1v rms and the other is a gain-controlled 2v rms max. the control range is between +12 and -26.75 db in steps of 1.25 db. this output can also be muted. a matrix is implemented to feed audio to and from decoders, vcrs and tvs. noise reduction system and de-emphasis can be inserted or by-passed through bus cont rol. also all the audio outputs are tri-state-type (high impedance mode is supported), allowing a simple parallel connections to the scarts (twin tuner applications).
circuit description stv0042a/z 14/37 2.0.3 other features a 22khz tone is generated for lnb control. it is selectable by bus control and ava ilable on one of the two pins connected to the external video de-emphasis networks. by means of the i 2 c bus there is the possibility to drive the ics into a low power consumption mode with active audio and video matrixes. independently from the main power mode, each individual audio and video output can be driven to high impedance mode.
15/37 stv0042a/z input/output diagrams 3 input/output diagrams figure 8: s2vidrtn and clampin pins 1 1. the 50 a source is active only when vidin < 2.7 v. figure 9: s1vidout and s2vidout pins 1 1. same as figure 8 , but with no black level adjustment. figure 10: videem1 pin 1 1. r on of the transistor gate is ? 10 k w . 50a 1a 10k w s2 vid rtn clamp in v dd 5v gnd 0v 1 1 v dd 9v 2.3ma gnd 0v 4 v cc 12v vid mux 10k w 20k w gnd 0v 60 w s1 vid out s2 vid out v ref 2.4v 20k w 1 125 a 6/2 10/2 v ideem1 figure 11: uncldeem pin 1 1. same as figure 9 , but with a slightly different gain. figure 12: fcl and fcr pins 1 1. i var is controlled by the maximum peak detection audio level 15 a (1 v pp audio). figure 13: s2outl and s2outr pins 1 1. same as figure 17 , but with gain fixed at +6 db. 2.3ma gnd 0v 4 v cc 12v in 10k w 16.7k w gnd 0v 60 w uncl deem v ref 2.4v 25k w fc l fc r 1 1 v dd 9 v ivar audio 2.4v bias 20k w gnd 0v s2 out l s2 out r 20k w
input/output diagrams stv0042a/z 16/37 figure 14: vidin pin figure 15: pkout pin figure 16: s2rtnl and s2rtnr pins 1 1. 4.8v bias voltage is the same as the bias level on the audio outputs. figure 17: voloutr and voloutl pins 1 1. audio output with volume and scart driver with +12 db gain for up to 2 v rms . the op amp has a push-pull output stage. v ref 2.4v vid in 6.5k w 10k w 85 a gnd 0v 1 0.5pf + v dd 9v audio pk out peak detector 5k w 3.4v clamp 1 1 50a 1 s2 rtn l s2 rtn r 4.8v 25k w audio 2.4v bias 30k w gnd 0v 30k w vol out r vol out l 15k w 4.8v figure 18: videem2 / 22khz pin 1 1. r on of the transistor gate is ? 10 k w . figure 19: fmin pin 1 1. the other input for each channel is internally biased in the same way via 10 k w to the 2.4 v vref. figure 20: iref pin 1 1. the optimum value if iref is 50 a 2% so an ext. resistor of 47.5 k w 1% is required. figure 21: detl and detr pins 1 1. i 2 - i 1 = f (phase error). 1 125a 6/2 10/2 videem2/22khz v dd 5v 100/2 60/2 22kh z 50a 1 fm in 2.4v 10k w 1 10k w left channel right channel 50a 1 2.4v i ref det l det r i1 i2
17/37 stv0042a/z input/output diagrams figure 22: scl pin 1 1. this is the input to a schmitt input buffer made with a cmos amplifier. figure 23: sda pin 1 1. input same as above. output pull down only, relies on external resistor for pull-up. figure 24: u75l and u75r pins 1 1. i 1 - i 2 = 2 x audio / 18 k w . e.g. 1 v pp audio: 55 a. there are internal switches to match the audio level of the different standards. figure 25: xtl pin scl 24/4 205 w esd sda 24/4 205 w esd 600/2 gnd 0v u75 l u75 r i2 i1 750a 460 w xtl gnd 0v 2 3 2 500a 5pf 460 w 3 750a figure 26: cpumpl and cpumpr pins 1 1. an offset on the pll loop filter will cause an offset in the two 1 a currents that will prevent the pll from drifting-off frequency. figure 27: amplkl, amplkr, agcl and agcr pins 1 1. i 2 and i 1 from the amplitude detecting mixer. figure 28: vref pin 1 1. the 400 a source is off during stand-by mode. cpump l cpump r vco input 1a 1a loop filter tracking 100a 100a dig synth v ref 2.4v amplk l a mplk r 10k w i1 2 i2 160a 5a agc l agc r to vca 4 vbg 1.2v v ref (2.4v) 10k w 10k w gnd 0v 400a
input/output diagrams stv0042a/z 18/37 figure 29: sumout pin figure 30: pkin pin 1 v ref 2.4v sumout 50k w 100a 49k w 49k w audio 1 v ref 2.4v pk in 67k w 100a to peak det figure 31: v12v, vgnd, vdd5v, gnd5v, agndl, a12v and agndr pins 1 1. refer to table 2 . v 12v v gnd video pads v dd 5v gnd 5v digital pads 205 w a gnd l a 12v a gnd r audio pads + bip 12v - substrate dzpn1 dzpn1 dzpn1 bip 10vpl vpp vmm table 2: double-buffered supply pins pin comment pad 1 pad 2 v12v double-bonded connected to all of the 12v esd and video guard rings connected to power up the video block vgnd double-bonded connected to power-up all of the video multiplexer and i/o. used only as a low noise gnd for the video input. vdd5v & gnd5v connected to the crystal oscillator and the bulk of the cmos logic and 5v esd. agndl double-bonded connected to the left vco, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. connected to both agc amps and the de-emphasis amplifiers, frequency synthesis and fm deviation selection circuit for both channels. a12v double-bonded connected to the esd and guard ring. connected to the main power for all of the audio parts. agndr double-bonded 1 connected to the right vco, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. connected to the bias block, audio noise reduction, volume, multiplexer and esd. 1. a third bond wire on this pin is connected directly to the die pad (substrate).
19/37 stv0042a/z i2c protocol 4 i2c protocol 4.1 writing to the chip s -start condition p -stop condition chip addr - 7 bits. 06h w write/read bit is the 8th bit of the chip address. a acknowledge after receiving 8 bits of data/address. reg addr address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are 'x' or don't care i.e. only the first 3 bits are used. data 8 bits of data being written to the register. all 8 bits must be written to at the same time. reg addr/a/data/a can be repeated, the write process can continue until terminated with a stop condition. if the reg addr is higher than 07 then iic protocol will still be met (i.e. an a generated). 4.2 reading from the chip when reading, there is an auto-increment feature. this means any read command always starts by reading reg 8 and will continue to read the following registers in order after each acknowledge or until there is no acknowledge or a stop. this function is cyclic that is it will read the same set of registers without re-addressing the chip. there are two modes of operation as set by writing to bit 7 of register 0. read 3 registers in a cyclic fashion or all 5 registers in a cyclic fashion. note only the last 5 of the 11 registers can be read. reg0 bit 7 = l ? start / chip add / r / a / reg 8 / a / reg 9 / a / reg 0a / a / reg 8 / a / reg 9 / a / reg 0a /... / p / reg0 bit 7 = h ? start / chip add / r / a / reg 8 / a / reg 9 / a / reg 0a / a / reg 7 / a / reg 6 / a / reg 8 / a / reg 9 / a / reg 0a / a / reg 7 / a / reg 6 / ... / p / table 3: example s 06 w a 00 a 55 a 01 a 8f ... a p
control registers stv0042a/z 20/37 5 control registers register 0 write only register 1 write only register 2 write only bit name reset function bit 7 0h read register 0: read 3 registers 1: read 5 registers bit 6 0h audio multiplexer - anrs noise reduction select (switch k3) (refer to figure 5 and figure 6 ) 0: anrs not active 1: anrs active bit 5 0h not to be used bits[4:0] 0h audio volume control select 00h: mute 01h: -26.75 db 1.25 db steps up to 1fh: +12 db bit name reset function bit 7 0h video de-emphasis 1 / video de-emphasis 2 0: video de-emphasis 1 1: video de-emphasis 2 bit 6 0h selected video invert 0: non-inverted 1: inverted bits[5:0] 0h select video gain 00h = 0 db 01h = +0.202 db 02h = +0.404 db 0.202 db steps up to 3fh = +12.73 db bit name reset function bits[7:6] 3h select left/right/stereo for volume output 00: mono left / channel 1 10: mono right / channel 2 11: stereo left and right (default) bits[5:4] 3h select audio source for volume output (switch k1) (refer to figure 5 and figure 6 ) 00: audio de-emphasis (switch k2 output) (position of switch k1: a) 10: scart 2 return (position of switch k1: c) 01: not to be used (position of switch k1: b) 11: high impedance or low power mode (default)
21/37 stv0042a/z control registers register 3 write only register 4 write only bit 3 0h select clock speed 0: 8 mhz 1: 4 mhz bits[2:0] 7h select video source for scart 1 output 000: baseband video 100: scart 1 return 001: de-emphasized video 101: not to be used 010: normal video 110: nothing selected 011: not to be used 111: high impedance or low power mode (default) bit name reset function bits[7:6] 3h audio de-emphasis select (switch k2) (refer to figure 5 and figure 6 ) 00: no de-emphasis (position of switch k2: a) 10: not to be used (position of switch k2: c) 01: 50 s de-emphasis (position of switch k2: b) 11: 75 s de-emphasis (position of switch k2: b) (default) bits[5:4] 3h select audio source for scart 2 output (switch k5) (refer to figure 5 and figure 6 ) 00: pll output (position of switch k5: c) 10: not to be used (position of switch k5: a) 01: audio de-emphasis (switch k2 output) (position of switch k5: b) 11: high impedance or low power mode (default) bit 3 0h 22 khz select 0: no tone 1: 22 khz tone out if bit 7 of register 1 = 0 bits[2:0] 7h select video source for scart 2 output 000: baseband video 100: scart 2 return 001: de-emphasized video 101: not to be used 010: normal video 110: nothing selected 011: not to be used 111: high impedance or low power mode (default) bit name reset function bits[7:4] dh not to be used. bit 3 1h standby or low power mode select 0: standby mode 1: low power mode bits[2:0] 7h not to be used. bit name reset function
control registers stv0042a/z 22/37 register 5 write only bit name reset function bits[7:6] 2h not to be used. bits[5:0] 35h fm deviation selection bit 5 = 0, double the fm deviation 110101: default value table 4: fm deviation selection table selected nominal carrier modulation bit 4 bit 3 bit 2 bit 1 bit 0 bit 5 = 1 bit 5 = 0 do not use. calibration setting = 0.3373 v offset on vco do not use. 0 0 0 0 0 do not use. calibration setting = 0.3053 v offset on vco do not use. 0 0 0 0 1 do not use. calibration setting = 0.2763 v offset on vco do not use. 0 0 0 1 0 calibration setting = 1 v offset on vco calibration setting (2 v) 0 0 0 1 1 296 khz 592 khz 0 0 1 0 0 267 khz 534 khz 0 0 1 0 1 242 khz 484 khz 0 0 1 1 0 218 khz 436 khz 0 0 1 1 1 198 khz 396 khz 0 1 0 0 0 179 khz 358 khz 0 1 0 0 1 161 khz 322 khz 0 1 0 1 0 146 khz 292 khz 0 1 0 1 1 133 khz 266 khz 0 1 1 0 0 120 khz 240 khz 0 1 1 0 1 109 khz 218 khz 0 1 1 1 0 98.3 khz 196 khz 0 1 1 1 1 89.7 khz 179 khz 1 0 0 0 0 80.9 khz 161 khz 1 0 0 0 1 73.1 khz 146 khz 1 0 0 1 0 66.0 khz 122 khz 1 0 0 1 1 60.0 khz 120 khz 1 0 1 0 0 54.4 khz (default) 109 khz 10101 49.1khz 98khz 10110 44.3khz 89khz 10111
23/37 stv0042a/z control registers register 6 write/read register 7 write/read 39.8khz 78khz 11000 35.9khz 71khz 11001 32.4khz 65khz 11010 29.1khz 58khz 11011 26.7khz 53khz 11100 24.3 khz 48.6 khz 1 1 1 0 1 21.9 khz 43.8 khz 1 1 1 1 0 19.7 khz 39.6 khz 1 1 1 1 1 bit name reset function bits[7:6] 2h select frequency for pll synthesizer bit 6: lsb (bit 0) of 10-bit value bit 7: bit 1 of 10-bit value bits[5:4] 0h select rf source x1: fm detector 1 enabled 1x: fm detector 2 enabled bits[3:2] 1h select frequency synthesizer x1: frequency synthesizer 1 enabled 1x: frequency synthesizer 2 enabled bit 1 1h i/o data direction select 0: input 1: output bit 0 0h i/o status bit name reset function bits[7:0] afh select frequency for pll synthesizer bit 0: bit 2 of 10-bit value bit 7: msb (bit 10) of 10-bit value table 4: fm deviation selection table selected nominal carrier modulation bit 4 bit 3 bit 2 bit 1 bit 0 bit 5 = 1 bit 5 = 0
control registers stv0042a/z 24/37 register 8 read only register 9 read only register 0a read only bit name reset function bits[7:6] read frequency of watchdog 2 bit 6: lsb (bit 0) of 10-bit value bit 7: bit 1 of 10-bit value bit 5 not to be used. bit 4 subcarrier detection (detector 2) 0: no subcarrier 1: subcarrier detected bits[3:2] read frequency of watchdog 1 bit 2: lsb (bit 0)of 10-bit value bit 3: bit 1 of 10-bit value bit 1 not to be used. bit 0 subcarrier detection (detector 1) 0: no subcarrier 1: subcarrier detected bit name reset function bits[7:0] read frequency of watchdog 1 bit 0: bit 2 of 10-bit value bit 7: msb (bit 10) of 10-bit value bit name reset function bits[7:0] read frequency of watchdog 2 bit 0: bit 2 of 10-bit value bit 7: msb (bit 10) of 10-bit value
25/37 stv0042a/z fm demodulation software routine 6 fm demodulation software routine with the stv0042a/z circuit, for each channel, three steps are required to achieve a fm demodulation: 1 to set the demodulation parameters: a fm deviation selection, a subcarrier frequency selection. 2 to implement a waiting loop to check the actual vco frequency. 3 to close the demodulation phase locked loop (pll). referring to figure 3: fm demodulation on page 6 , the frequency synthesis block is common to both channels (left and right); consequently two complete sequences have to be done one after the other when demodulating stereo pairs. 6.1 detailed description conventions: l r = stands for register l b = stands for bit example: r5b2 = register 5, bit 2 for clarity, the explanations are based on the following example: stereo pair 7.02 mhz/l and 7.20 mhz/r and 50 khz maximum deviation 6.1.1 1st step (left): setting the demodulation parameters 1 the fm deviation is selected by loading register 5 with the appropriate value. corresponding bandwidth can be calculated as follows: bw ? 2 (fm deviation and audio bandwidth) bw ? 2 (value given in table and audio bandwidth) in the example: note: very wide deviations (up to 592 khz) can be accommodated when r5b5 is low. 2 the subcarrier frequency is selected by launching a frequency synthesis (the vco is driven to the desired frequency). this operation requires two actions: 2.1 connect the vco to the frequency synthesis loop. see figure 3 on page 6 . a switch k4 closed ? r6 b2 = 1 a switch k3 to bias ? r6 b4 = 0 a switch k2 to bias ? r6 b3 = 0 a switch k1 open ? r6 b5 = 0 r5 bits 7 6 5 4 3 2 1 0 x x 1 1 0 1 1 0
fm demodulation software routine stv0042a/z 26/37 2.2 load r7 b[7:0] and r6 b[7:6] with the values corresponding to the left channel frequency. this 10 bits value is calculated as follows: subcarrier frequency = coded value x 10 khz (10 khz is the m inimum step of the frequency synthesis function). since the tuning range is between 5 and 10 mhz, the coded value is a number between 500 and 1000 (210 = 1024). this value is coded on 10 bits. example : 7.02 mhz = 702 x 10 khz 702 ? 1010 1111 10 ? af + 10 r7 is loaded with af and r6 b6: 0, r6 b7: 1. table 5 gives the settings for the most common subcarrier frequencies. 6.1.2 2nd step (left): vco frequency checking (vco) this second step is actually a waiting loop in which the actual running frequency of the vco is measured. this loop can be exited when: subcarrier frequency - 10 khz measured frequency subcarrier frequency +10 khz where, 10 khz is the maximum dispersion of the frequency synthesis function). in practice, r8 b[3:2] and r9 b[7:0] are read and compared to the value loaded in r6 b[7:6] and r7 b[7:0] 1 bit. the duration of this step depends on the difference between the start frequency and the targeted frequency. typically: l the rate of change of the vco frequency is about 3.75 mhz/s (pin cpump = 10 f) l in addition to this settling time, 100 ms must be added to take into account the sampling period of the watchdog. 6.1.3 3rd step (left) the fm demodulation can be started by connecting the vco to the phase locked loop (pll). in practice: l switch k3 closed ? r6 b4 = 1 l switch k4 open ? r6 b2 = 0 after this sequence of 3 steps for left channel, a similar sequence is required for the right channel. note: 1 the fm deviation does not have to be selected again for the right channel (once is enough for the pair). 2 before sending the demodulated signal to the audio output, it is recommended to keep the muting and to check whether a subcarrier is present at the desired frequency. such information can be read in r8 b0 and r8 b4. two different strategies can be adopted when enabling the output: l either both left and right demodulated signals are simultaneously authorized when both channels are ready. l or while the right channel sequence is running, the already ready left signal is sent to the left and right outputs and the real stereo sound l/r is output when both channels are ready. this second option outputs the sound a few hundred milliseconds before the first one.
27/37 stv0042a/z fm demodulation software routine table 5: frequency synthesis register setting for the most common subcarrier frequencies subcarrier frequency (mhz) register 7 (hex) register 6 bit 7 bit 6 5.58 8b 1 0 5.76 90 0 0 5.8 91 0 0 5.94 94 1 0 6.2 9b 0 0 6.3 9d 1 0 6.4 a0 0 0 6.48 a2 0 0 6.5 a2 1 0 6.6 a5 0 0 6.65 a6 0 1 6.8 aa 0 0 6.85 ab 0 1 7.02 af 1 0 7.20 b4 0 0 7.25 b5 0 1 7.38 b8 1 0 7.56 bd 0 0 7.74 c1 1 0 7.85 c4 0 1 7.92 c6 0 0 8.2 cd 0 0 8.65 d8 0 1
application diagrams stv0042a/z 28/37 7 application diagrams figure 32: typical stv0042a/z application diagram with 2 video de-emphasis networks stv0042a/z c6 4 1.5nf r 5 8 4 3k v cc v q 1 b c 5 4 7 tv s c a r t 1 2 3 4 5 6 7 8 9 1 0 1 6 1 7 1 8 1 9 2 0 11 1 2 1 3 1 4 15 2 1 2 9 3 0 3 6 3 7 3 8 4 0 3 1 3 2 33 3 4 3 5 3 9 4 1 4 2 2 8 2 7 2 6 2 5 2 4 2 3 22 jp 5 jp 8 jp 1 0 jp 9 r 5 7 2 4 k c6 3 22 0 nf r 5 4 3 . 3k c6 2 8 . 2 nf r 55 1.5 k c6 1 1.5nf q 4 b c 55 7 r 5 6 1 0 k v cc a jp 7 r 5 3 4 3k c6 0 1.5nf c 5 8 1 00 nf r 5 0 4 7 .5 k 1 % c 5 0 1 0 f 1 6 v + r 3 7 5 6 0 k c 4 5 1 00 nf v cc a r 51 5 6 0 k r 4 0 1 8 0 k c 4 7 22 p f c 4 8 22 p f r 4 1 8 2 k c 4 6 2 . 7 nf r 3 9 2 7 k c 4 0 4 7 0 f 1 6 v + c 4 3 1 00 nf r 3 6 5 6 0 k c 4 2 1 00 nf c 3 9 2 . 7 nf r 3 4 2 7 k r 33 1 8 0 k c 3 8 22 p f c 3 7 22 p f r 3 2 8 2 k c 4 1 1 0 f 1 6 v + v dd c 2 9 22 p f jp 2 1 2 3 4 jp 6 c66 4 7 p f j 1 0 5 v s d a s c l gn d 1 1 i/ o c l o c k i n p u t j 9 j 8 1 1 5 v gn d j 1 2 j 1 1 l 1 22 h + c 3 1 22 0 f 1 6 v c 3 0 1 00 nf v dd 1 1 1 2 v gn d j 1 4 j 1 3 l 2 22 h + c 33 22 0 f 1 6 v c 3 2 1 00 nf v cc v + c 3 5 22 0 f 1 6 v c 3 4 1 00 nf v cc a 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 15 1 6 1 7 1 8 1 9 2 0 2 1 j 1 j 6 r j 5 l j 4 v r 2 6 8 r 3 4 7 0 c 2 2 . 2 f c 3 2 . 2 f jp 11 v cc v q 2 b c 5 4 7 r 4 4 7 0 v cc v jp 1 c 5 6 1 00 nf c 2 3 8 . 2 nf c 2 4 2 7 p f r 1 7 4 7 0 r 1 8 1 k l 4 4 7 h c 2 5 1 00 p f r 4 8 7 5 c 2 6 1 0 f 1 6 v j 7 t u n e r i n p u t c 1 2 1 00 p f r 9 5.1 k c 1 4 15 0 p f r 1 4 5. 6 k + c 1 3 1 0 f 1 6 v r 11 1.5 k r 1 0 1 0 k r 1 2 1. 8 k r 1 3 1 0 k + c 15 1 0 f 1 6 v c 5 2 . 2 f v cr / de c ode r s c a r t 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 15 1 6 1 7 1 8 1 9 2 0 2 1 j 2 r 5 6 8 c6 2 . 2 f c 8 2 . 2 f c 7 2 . 2 f c 11 8 . 2 nf r 1 6 1 k 3 2 1 t d k f i l t e r s e l 5 6 1 8 r 15 1 k r 6 7 5 c 4 22 0 nf o p tio n ally : a sec o n d v i de o deem p h a s i s n e t w o r k r 1 3 , r 1 2 , c 15 , r 1 4 , c 1 4 i s sh o w n f o r 5 2 5 li n es s y s t ems . s e l 5 6 1 8 : 5 m h z l p f m a de b y t d k / j a p a n c6 5 4 7 p f 4 m h z o r 8 m h z c r y s tal r 6 0 1. 2 m c66 1 00 nf c6 5 1 00 nf r 5 9 1. 2 m 8 . 2 v 8 . 2 v ! ! ! v er y i m p o r a n t ! 8 . 2 v z e n er d io des o n p i n s 2 7 a n d 3 8 a re rec o mme n ded to p reve n t a f al se lo c k i n g i n c a se o f ver y m a r g i n al c o n d itio n s .
29/37 stv0042a/z application diagrams figure 33: typical stv0042a/z application diagram with 22 khz and 3 audio de-emphasis networks 8.2v stv0042 a/z c6 4 1 . 5nf r 5 8 4 3 k v cc v q 1 b c 5 4 7 tv s c a r t 1 2 3 4 5 6 7 8 9 1 0 1 6 1 7 1 8 1 9 2 0 11 1 2 1 3 1 4 15 2 1 2 9 3 0 3 6 3 7 3 8 4 0 3 1 3 2 33 3 4 3 5 3 9 4 1 4 2 28 2 7 2 6 2 5 2 4 2 3 22 jp 5 jp 8 jp 1 0 jp 9 r 5 7 2 4 k c6 3 22 0 nf r 5 4 3 . 3 k c6 2 8.2 nf r 55 1 . 5 k c6 1 1 . 5nf q 4 b c 55 7 r 5 6 1 0 k v cc a jp 7 r 5 3 4 3 k c6 0 1 . 5nf c 5 8 1 00 nf 4 7 . 5 k - 1 % c 5 0 1 0 f 1 6 v + r 3 7 5 6 0 k c 4 5 1 00 nf v cc a r 51 5 6 0 k r 4 0 1 8 0 k c 4 7 22 p f c 4 8 22 p f r 4 1 82 k c 4 0 4 7 0 f 1 6 v + c 4 3 1 00 nf r 3 6 5 6 0 k c 4 2 1 00 nf r 33 1 8 0 k c 3 8 22 p f c 3 7 22 p f r 3 2 82 k c 4 1 1 0 f 1 6 v + v dd c 2 9 22 p f jp 2 1 2 3 4 jp 6 c66 4 7 p f j 1 0 5 v s d a s c l gn d 1 1 i/ o c l o c k i n p u t j 9 j 8 1 1 5 v gn d j 1 2 j 1 1 l 1 22 h + c 3 1 22 0 f 1 6 v c 3 0 1 00 nf v dd 1 1 1 2v gn d j 1 4 j 1 3 l 2 22 h + c 33 22 0 f 1 6 v c 3 2 1 00 nf v cc v + c 3 5 22 0 f 1 6 v c 3 4 1 00 nf v cc a 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 15 1 6 1 7 1 8 1 9 2 0 2 1 j 1 j 6 r j 5 l j 4 v r 2 6 8 r 3 4 7 0 c 2 2.2 f c 3 2.2 f jp 11 v cc v q 2 b c 5 4 7 r 4 4 7 0 v cc v jp 1 c 5 6 1 00 nf c 2 3 8.2 nf c 2 4 2 7 p f r 1 7 4 7 0 r 1 8 1 k l 4 4 7 h c 2 5 1 00 p f r 4 8 7 5 c 2 6 1 0 f 1 6 v j 7 t u n e r i n p u t c 1 2 1 00 p f r 9 5 . 1 k + c 1 3 1 0 f 1 6 v r 11 1 . 5 k r 1 0 1 0 k c 5 2.2 f v cr / de c ode r s c a r t 1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 1 4 15 1 6 1 7 1 8 1 9 2 0 2 1 j 2 r 5 6 8 c6 2.2 f c 8 2.2 f c 7 2.2 f c 11 8.2 nf r 1 6 1 k 3 2 1 t d k f i l t e r s e l 5 6 1 8 r 15 1 k r 6 7 5 c 4 22 0 nf o p tio n ally : a sec o n d v i de o deem p h a s i s n e t w o r k r 1 3 , r 1 2 , c 15 , r 1 4 , c 1 4 i s sh o w n f o r 5 2 5 li n es s y s t ems . s e l 5 6 1 8 : 5 m h z l p f m a de b y t d k / j a p a n c6 5 4 7 p f 4 m h z o r 8 m h z c r y s tal r 6 0 1 .2 m c66 1 00 nf c6 5 1 00 nf r 5 9 1 .2 m 22 k h z t o n e 2 7 k 2. 7 nf r 5 0 7 5 / j 1 7 8.2 nf 4 . 7 k 3 6 k 4 . 7 k 4 . 7 k 4 . 7 k 3 6 k 4 . 7 k 8.2 nf 2 7 k 2. 7 nf 8.2v ! v er y i m p o r a n t ! 8.2v z e n er d io des o n p i n s 2 7 a n d 3 8 a re rec o mme n ded to p reve n t a f al se lo c k i n g i n c a se o f ver y m a r g i n al c o n d itio n s . ! !
electrical characteristics stv0042a/z 30/37 8 electrical characteristics 8.1 absolute maximum ratings 8.2 thermal data 8.3 electrical characteristics test conditions: t amb = 25c, v cc = 12 v and v dd = 5 v; unless otherwise specified. 8.3.1 clamp stages (pins clampin and s2vidrtn) symbol parameter value unit v cc v dd supply voltage 15.0 7.0 v p tot total power dissipation 900 mw symbol parameter value unit r thja junction-to-ambient thermal resistance 60 c/w t oper operating ambient temperature 0 to +70 c t stg storage temperature - 55 to +150 c symbol parameter test conditions min. typ. max. unit v cc v dd supply voltage 11.4 4.75 12.0 5.0 12.6 5.25 v iq cc iq dd supply current all audio and video outputs active. 55 8 70 15 ma iqlp cc iqlp dd supply current at low power mode all audio and video outputs in high impedance mode. 27 6 35 9 ma symbol parameter test conditions min. typ. max. unit iskc clamp input sink current v in = 3 v 0.5 1.0 1.5 a iscc clamp input source current v in = 2 v 40 50 60 a
31/37 stv0042a/z electrical characteristics 8.3.2 audio demodulator 8.3.3 automatic noise reduction system symbol parameter test conditions min. typ. max. unit fmin fm subcarrier input level (fmin pin for agc action) vco locked on carrier at 6 mhz 560 k w load on amplk pins 180 k w load on det pins 5 500 mv pp deth detector 1 and 2 (amplk pins) (threshold for activating level detector 2) 8mv pp fmin 500 mv pp carrier without modulation 2.90 3.10 3.30 v vco min vco minimum frequency v cc = 11.4 to 12.6 v t amb = 0 to +70 c 5mhz vco max vco maximum frequency v cc = 11.4 to 12.6 v t amb = 0 to +70 c 10 mhz ap50 1 khz audio level at pll output (det pins) 50 khz dev. fm input at 0.5 v pp coarse deviation set to 50 khz. (reg. 05 = 36h) 0.6 1.0 1.35 v pp apa50 1 khz audio level at pll output (det pins) 50 khz dev. fm input at 0.5 v pp coarse and fine settings used. 0.92 1.0 1.08 v pp fmbw fm demodulator bandwidth gain at 12 khz versus 1 khz 180 k w , 82 k w and 22 pf on det pins. 0.0 0.3 1.0 db dpco digital phase comparator output current (cpump pins) average sink and source current to external capacitor. 60 a symbol parameter test conditions min. typ. max. unit lrs output level (sumout pin) 1v pp on left and right channels. 0.9 1.0 1.1 v pp ldor level detector output resistance (pkout pins) 4.0 5.4 6.8 k w ndft level detector fall time constant (pkout pins) external 22 nf to gnd and 1.2 m w to vref. 26.4 ms ndll bias level (pkout pins) no audio inputs. 2.4 v llcf noise reduction cut-off frequency at low level audio 100 mv pp on det pins, external 330 pf capacitor on fc pins. 0.85 khz hlcf noise reduction cut-off frequency at high level audio 1v pp on det pins, external 330 pf capacitor on fc pins. 7.00 khz
electrical characteristics stv0042a/z 32/37 8.3.4 audio outputs (pins voloutr and voloutl) 8.3.5 auxiliary audio outputs (pins s2outr and s2outl) symbol parameter test conditions min. typ. max. unit dcol dc output level 4.8 v aoln audio output level (reg 00 = 1ah) fm input same as apa50, no de-emphasis, no pre- emphasis and no noise reduction. 1.50 1.90 2.34 v pp aol50 audio output level (reg 00 = 1ah) fm input same as apa50, 50 s de-emphasis, 27 k w and 2.7 nf load, no pre-emphasis and no noise reduction. 2.0 3.3 4.0 v pp aol75 audio output level (reg 00 = 1ah) fm input same as apa50, 75 s de-emphasis, 27 k w and 2.7 nf load, no pre-emphasis and no noise reduction. 2.0 3.3 4.0 v pp ama1 audio output attenuation with mute on (reg 00 = 00h) 1khz at 1v pp from s2rtn pins. 60 65 db mxat maximum attenuation before mute (reg 00 = 01h) 1 khz from s2rtn pins. 32.75 db mxag audio gain (reg 00 = 1fh) 1 khz from s2rtn pins. 5 6 7 db astp attenuation of each of the 31 steps 1 khz 1.25 db thda1 thd with reg00 = 1ah 1khz at 1v pp from s2rtn pins. 0.15 % thda2 thd with reg00 = 1ah 1khz at 2v pp from s2rtn pins. 0.3 1.0 % thdafm thd with reg00 = 1ah fm input same as apa50, 75 s de-emphasis, anrs on. 0.3 1.0 % acs audio channel separation 1khz at 1v pp from s2rtn pins. 60 74 db acsfm audio channel separation at 1 khz 0.5 v pp and 50 khz deviation fm input on one channel, 0.5v pp no deviation fm input on the other channel, reg 05 = 36h, 75 ms de- emphasis, no anrs 60 db snfm signal-to-noise ratio fm input same as apa50, 75 s de-emphasis, anrs off, unweighted. 56 db snfmnr signal-to-noise ratio fm input same as apa50, 75 s de-emphasis, anrs on, unweighted. 69 db z outl z outh audio output impedance low impedance mode high impedance mode 30 18 44 55 w k w symbol parameter test conditions min. typ. max. unit dcolao dc output level auxiliary input pins in open circuit 4.8 v aolns audio output level on s2 fm input same as apa50, no de-emphasis, no pre- emphasis and no noise reduction. 1.55 2.00 2.42 v pp
33/37 stv0042a/z electrical characteristics 8.3.6 reset threshold 8.3.7 video matrix (pins s1vidout and s2vidout) 8.3.8 composite signal processing aol50s audio output level on s2 fm input same as apa50, 50 s de-emphasis, 27 k w and 2.7 nf load, no pre-emphasis and no noise reduction. 2.0 3.4 4.0 v pp aol75s audio output level on s2 fm input same as apa50, 75 s de-emphasis, 27 k w and 2.7 nf load, no pre-emphasis and no noise reduction. 2.0 3.4 4.0 v pp thdaofm thd on s2 fm input same as apa50, 75 s de-emphasis, anrs on. 0.3 1.0 % z outl z outh audio output impedance low impedance mode high impedance mode 30 60 44 100 55 w k w symbol parameter test conditions min. typ. max. unit rtccu end of reset threshold for v cc v dd = 5 v, v cc rising 8.7 v rtccd start of reset threshold for v cc v dd = 5 v, v cc falling 7.9 v rtddu end of reset threshold for v dd v cc = 12 v, v dd rising 3.8 v rtddd start of reset threshold for v dd v cc = 12 v, v dd falling 3.5 v symbol parameter test conditions min. typ. max. unit xtk output level on any output when 1 vpp cvbs input is selected for any other output 5mhz -60 db bfg output buffer gain 100 khz 1.87 2.0 2.13 dcolvh dc output level high impedance mode 0.0 0.2 v z outhv video output impedance high impedance mode 16 23 30 k w vcl sync tip level on selected outputs 1v pp cvbs via 10 nf on input 1.05 1.30 1.55 v symbol parameter test conditions min. typ. max. unit vidc vidin voltage external load current < 1 a 2.25 2.45 2.65 v zvi vidin input impedance 7 11 14 k w deodc dc output level (videem pins) 2.25 2.45 2.65 v deomx maximum ac level before clipping (videem pins) gv = 0 db, reg 01 = 00h 2 v pp symbol parameter test conditions min. typ. max. unit
electrical characteristics stv0042a/z 34/37 dgv gain error versus gv at 100 khz gv = 0 to 12.7 db, reg 01 = 00h to 3fh -0.5 0 0.5 db invg inverter gain -0.9 -1.0 -1.1 visog video input to scart output gain de-emphasis amplifier mounted in unity gain, normal video selected. -1 0 1 db debw bandwidth for 1 v pp input measured on videem pins -3 db with gv = 0 db, reg 01 = 00h 10 mhz dfg differential gain on sync pulses measured on videem pins gv = 0db, 1v pp cvbs +0.5 v pp 25 hz sawtooth (vidin input) 1% itmod intermodulation of fm subcarriers with chroma subcarrier 7.02 and 7.2 mhz subcarriers, 12.2 db lower than chroma -60 db symbol parameter test conditions min. typ. max. unit
35/37 stv0042a/z package mechanical data 9 package mechanical data figure 34: 42-pin shrink plastic dual in-line package, 600-mil width dim. mm inches min. typ. max. min. typ. max. a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 0.00 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140
revision history stv0042a/z 36/37 10 revision history revision main changes date 0.1 first issue. june 2001 1.0 revised issue. pin names icath and vout are confirmed. document format updated. january 2002 1.1 addition of stv0042z sales type and included information in section 1.1.1.5: fm pll charge pump capacitors on page 6 july 2002 1.2 modification of figure 3: fm demodulation , figure 32: typical stv0042a/z application diagram with 2 video de-emphasis networks , figure 33: typical stv0042a/z application diagram with 22 khz and 3 audio de-emphasis networks , section 1.1.1.5: fm pll charge pump capacitors and information in section 5: control registers . 30 july 2002
37/37 stv0042a/z information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information pr eviously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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